搜索资源列表
vhdlcode
- VHDL code in ISE (for collecting the ADC samples from kit and for viewing final output)
dividefreq
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
Leds
- Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
DDRIO
- Xilinx公司开发板中的一个模块，在时钟的上升和下降沿同时传输数据。使用时需要在ISE集成开发环境下利用VHDL进行例化。本文是对该模块功能的说明，是个人的学习总结-Xilinx has developed a module board, in the clock' s rising and falling at the same time transmission of data. ISE needs to use integrated development environment
lab_text
- EDA考试的五种题目编程，其中包括五人表决器，抢答器，乘法器，自动售货机等， 编译环境为ISE，程序语言VHDL-eda text ise vhdl
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
nbit_Comp
- This file is a Nbits comparator which was developed by ISE. and is writen in VHDL.
DesignofFloatingPointCalculatorBasedonFPGA
- 给出系统的整体框架设计和各模块的实现，包括芯片的选择、各模块之间的时序以及控制、每个运算模块详细的工作原理和算法设计流程；通过VHDL语言编程来实现浮点数的加减、乘除和开方等基本运算功能；在Xilinx ISE环境下，对系统的主要模块进行开发设计及功能仿真，验证 了基于FPGA的浮点运算。 -The overall framework of system design and realization of each module which contain selection of ch
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
MD_DDS_10bit_VHDL
- 十位DA输出的DDS，用VHDL实现，环境：ISE 8.1，仿真软件：ModelSim_SE_6.1b-10 DA output of the DDS, with the VHDL implementation, environment: ISE 8.1, simulation software: ModelSim_SE_6.1b
adder
- adder in vhdl , ff , using xilinx ise -adder in vhdl , ff , using xilinx ise
BasysDemo_ISEproject
- 使用ISE继承开发环境，vhdl语言编写的Basys开发板测试程序-Basys test
cangyongEDAgjzn
- 4.1 Altera MAX+plusⅡ操作指南 4.1.1 MAX+plusⅡ10.2的安装 4.1.2 MAX+plusⅡ开发系统设计入门 4.2 Xilinx ISE Series的使用 4.2.1 ISE的安装 4.2.2 ISE工程设计流程 4.2.3 VHDL设计操作指南 4.2.4 ISE综合使用实例 4.3 Lattice ispDesignEXPERT的使用 4.3.1 ispDesignEXPERT的安装 4.3.2 原理图输入方式设计
comm
- 串口通信电路VHDL描述，采用ISE环境开发-VHDL descr iption of serial communication circuits
00
- 用VHDL语言调用IP核，在ISE中实现三角波-VHDL IP core with the realization of the triangular wave is called
VHDL_simple_settable_clock
- 基于Xilinx ISE软件的用VHDL编写的一个简易的可调节时钟，具有时、分、秒功能-Xilinx ISE based,a simple settable clock using VHDL, with hours, minutes, seconds functions
clock
- XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the
multiplier
- this document describe a 8 * 8 bits mutiplier with vhdl using booth algorithm and shown all parts of implementing this ip by ise software
example9
- xilinx的ISE下，VHDL语言实现简单的vga显示红绿相间的条纹-xilinx under the ISE, VHDL language simple vga display red and green stripes